30th Annual Student Research Conference
Design and Implementation of a Hybrid AES-SHA 3 Crypto Processor on a Field Programmable Gate Array
Ronit Das
Dr. John Seiffertt, Faculty Mentor
With the rapid progression of data exchange in the electronic world, information security is becoming more important in data transmission and storage. Security becomes a serious issue during the transmission of confidential information. Cryptographic algorithms are used to scramble texts from one form to another . This research presents the novel design and implementation of a hybrid crypto processor implementing the Advanced Encryption Standard (AES) encryption algorithm coupled with the Secured Hashing Algorithm 3 (SHA 3) hashing function on a soft-core processor. AES is a block cipher, symmetric-key algorithm that uses a single key for both encryption and decryption. Encrypting a message does not guarantee that this message is not changed while encrypted. With our implementation of SHA 3, Message Authentication Code (MAC) generation can be done very easily with no HMAC nested construction which makes AES more secure, and makes the system more resistant against side-channel attacks.
Keywords: Advanced Encryption Standard (AES), Secured Hashing Algorithm 3 (SHA 3), Message Authentication Code (MAC), crypto processor, block cipher, symmetric-key algorithm, hashing function, side-channel attacks
Topic(s):Computer Science
Presentation Type: Oral Paper
Session: 312-4
Location: VH 1320
Time: 1:45