Crypto Graphic Processors

Ronit Das
Dr. John Seiffertt, Faculty Mentor

This paper presents a fully pipelined architecture for the AES 128 encryption and decryption algorithm on an FPGA. The implementation is only for CFB, OFB, and CTR modes of confidentiality and our architecture is a very compact design since the decryption unit is no longer needed. The design is simulated on Xilinx’s Artix-7 family of FPGA’s using Xilinx Vivado 2017.2 HLx WebPack Design Suite. The byte substitution phase is implemented in block RAMs. Every round is pipelined for the encryption unit, as well as the key expansion unit. The design utilizes loop unrolling, thereby achieving a high throughput of 43.75 Gbps while using only 2231 slices of the FPGA with a latency of 41 clock cycles, a throughput-per-area rate of 19.6 Mbps/slice and a performance-per-Watt of 21.9 Gbps/W.

Keywords: Field Programmable Gate Array, Advanced Encryption Standard, cryptography, network security, achitecture

Topic(s):Computer Science

Presentation Type: Oral Paper

Session: 309-5
Location: VH 1212
Time: 2:00

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